How to use quartis 2 for simulating verilog files and drawing timing diagrams

Open quartis 2 - create a new project with the needed specs as guided by the wizard

1. New project
Now right click in the in the files tab and create a new verilog HDL file and give and set it as main project

2. Type verilog code & compile
now type your sample verilog code
the file name and the module name should be the same
then in tools tab in menu bar select compile code.

3. Creating .vwf file
Now create a new -> vector wave form (.vwf) file by right clicking the in files tab
In the .vwf file,
there will be 2 columns.

4. Input to .vwf file
On the left column right click and select - > node finder
In node finder dialog box - > select all pins from the drop down list
Now,
click the button list
output: it will list all the input and output pins available

Now select the >> symbol to move the items from the left column to the right column and select OK button.

5. Now the left column of the .vwf file will be filled with input and output pins

6. now select each pin - > right click and select values -> random value


7. select your value of desired choice.

8. Now in tools menu go to simulation tool option
  select functional simulation
select the check box which says overwrite input file with output file.
click on generate functional simulation netlist button


9. Now click start simulation button at the bottom.

10. Now if you select the vector wave form file it will have the output.

11. For viewing the circuit diagram you can use RTL viewer present in viewers menu entry in simulation menu.